{"publication_status":"published","user_id":"220548","page":"1-4","author":[{"full_name":"Vohrmann, Marten","last_name":"Vohrmann","first_name":"Marten"},{"full_name":"Geisler, Philippe","first_name":"Philippe","last_name":"Geisler"},{"orcid":"0000-0001-7425-8766","full_name":"Jungeblut, Thorsten","id":"242294","first_name":"Thorsten","last_name":"Jungeblut","orcid_put_code_url":"https://api.orcid.org/v2.0/0000-0001-7425-8766/work/157789062"},{"first_name":"Ulrich","last_name":"Ruckert","full_name":"Ruckert, Ulrich"}],"title":"Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology","publisher":"IEEE","language":[{"iso":"eng"}],"date_updated":"2024-04-17T07:35:09Z","conference":{"end_date":"2017-09-06","name":"2017 European Conference on Circuit Theory and Design (ECCTD)","start_date":"2017-09-04","location":"Catania"},"_id":"4488","citation":{"bibtex":"@inproceedings{Vohrmann_Geisler_Jungeblut_Ruckert_2017, title={Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology}, DOI={<a href=\"https://doi.org/10.1109/ECCTD.2017.8093232\">10.1109/ECCTD.2017.8093232</a>}, booktitle={2017 European Conference on Circuit Theory and Design (ECCTD)}, publisher={IEEE}, author={Vohrmann, Marten and Geisler, Philippe and Jungeblut, Thorsten and Ruckert, Ulrich}, year={2017}, pages={1–4} }","apa":"Vohrmann, M., Geisler, P., Jungeblut, T., &#38; Ruckert, U. (2017). Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology. In <i>2017 European Conference on Circuit Theory and Design (ECCTD)</i> (pp. 1–4). Catania: IEEE. <a href=\"https://doi.org/10.1109/ECCTD.2017.8093232\">https://doi.org/10.1109/ECCTD.2017.8093232</a>","ama":"Vohrmann M, Geisler P, Jungeblut T, Ruckert U. Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology. In: <i>2017 European Conference on Circuit Theory and Design (ECCTD)</i>. IEEE; 2017:1-4. doi:<a href=\"https://doi.org/10.1109/ECCTD.2017.8093232\">10.1109/ECCTD.2017.8093232</a>","alphadin":"<span style=\"font-variant:small-caps;\">Vohrmann, Marten</span> ; <span style=\"font-variant:small-caps;\">Geisler, Philippe</span> ; <span style=\"font-variant:small-caps;\">Jungeblut, Thorsten</span> ; <span style=\"font-variant:small-caps;\">Ruckert, Ulrich</span>: Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology. In: <i>2017 European Conference on Circuit Theory and Design (ECCTD)</i> : IEEE, 2017, S. 1–4","chicago":"Vohrmann, Marten, Philippe Geisler, Thorsten Jungeblut, and Ulrich Ruckert. “Design-Space Exploration of Ultra-Low Power CMOS Logic Gates in a 28 Nm FD-SOI Technology.” In <i>2017 European Conference on Circuit Theory and Design (ECCTD)</i>, 1–4. IEEE, 2017. <a href=\"https://doi.org/10.1109/ECCTD.2017.8093232\">https://doi.org/10.1109/ECCTD.2017.8093232</a>.","mla":"Vohrmann, Marten, et al. “Design-Space Exploration of Ultra-Low Power CMOS Logic Gates in a 28 Nm FD-SOI Technology.” <i>2017 European Conference on Circuit Theory and Design (ECCTD)</i>, IEEE, 2017, pp. 1–4, doi:<a href=\"https://doi.org/10.1109/ECCTD.2017.8093232\">10.1109/ECCTD.2017.8093232</a>.","ieee":"M. Vohrmann, P. Geisler, T. Jungeblut, and U. Ruckert, “Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology,” in <i>2017 European Conference on Circuit Theory and Design (ECCTD)</i>, Catania, 2017, pp. 1–4.","short":"M. Vohrmann, P. Geisler, T. Jungeblut, U. Ruckert, in: 2017 European Conference on Circuit Theory and Design (ECCTD), IEEE, 2017, pp. 1–4."},"publication":"2017 European Conference on Circuit Theory and Design (ECCTD)","year":"2017","publication_identifier":{"eisbn":["978-1-5386-3974-0"]},"status":"public","type":"conference","date_created":"2024-04-16T10:32:17Z","doi":"10.1109/ECCTD.2017.8093232"}