Malicious Routing: Circumventing Bitstream-level Verification for FPGAs
Q.A. Ahmed, T. Wiersema, M. Platzner, in: IEEE (Ed.), 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, 2021, pp. 1490–1495.
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Konferenzbeitrag
| Veröffentlicht
| Englisch
Autor*in
Ahmed, Qazi Arbab
;
Wiersema, Tobias;
Platzner, Marco
;
Wiersema, Tobias;
Platzner, Marcoherausgebende Körperschaft
IEEE
Erscheinungsjahr
Titel des Konferenzbandes
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Seite
1490-1495
Konferenz
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Konferenzort
Grenoble, France
Konferenzdatum
2021-02-01 – 2021-02-05
FH-PUB-ID
Zitieren
Ahmed, Qazi Arbab ; Wiersema, Tobias ; Platzner, Marco: Malicious Routing: Circumventing Bitstream-level Verification for FPGAs. In: IEEE (Hrsg.): 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) : IEEE, 2021, S. 1490–1495
Ahmed QA, Wiersema T, Platzner M. Malicious Routing: Circumventing Bitstream-level Verification for FPGAs. In: IEEE, ed. 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE; 2021:1490-1495. doi:10.23919/DATE51398.2021.9474026
Ahmed, Q. A., Wiersema, T., & Platzner, M. (2021). Malicious Routing: Circumventing Bitstream-level Verification for FPGAs. In IEEE (Ed.), 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 1490–1495). Grenoble, France: IEEE. https://doi.org/10.23919/DATE51398.2021.9474026
@inproceedings{Ahmed_Wiersema_Platzner_2021, title={Malicious Routing: Circumventing Bitstream-level Verification for FPGAs}, DOI={10.23919/DATE51398.2021.9474026}, booktitle={2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, publisher={IEEE}, author={Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco}, editor={IEEEEditor}, year={2021}, pages={1490–1495} }
Ahmed, Qazi Arbab, Tobias Wiersema, and Marco Platzner. “Malicious Routing: Circumventing Bitstream-Level Verification for FPGAs.” In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), edited by IEEE, 1490–95. IEEE, 2021. https://doi.org/10.23919/DATE51398.2021.9474026.
Q. A. Ahmed, T. Wiersema, and M. Platzner, “Malicious Routing: Circumventing Bitstream-level Verification for FPGAs,” in 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2021, pp. 1490–1495.
Ahmed, Qazi Arbab, et al. “Malicious Routing: Circumventing Bitstream-Level Verification for FPGAs.” 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), edited by IEEE, IEEE, 2021, pp. 1490–95, doi:10.23919/DATE51398.2021.9474026.
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